1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices, and more particularly to, a method for forming a Metal-Oxide-Semiconductor devices having reverse-offset spacer.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductors, become highly integrated, the area occupied by the devices shrinks, as well as the design rule.
A cross-sectional view of a Metal-Oxide-semiconductor device of the know prior art is illustrated in FIG. 1. A semiconductor substrate 20 is a silicon substrate. The semiconductor substrate includes shallow trench isolation 22, and which collocates to form a gate oxide layer 24 and a gate 26 on the surface of the semiconductor substrate 20. Lightly doping drain regions 30 formed in the semiconductor substrate 20 after an ion implantation is performed, and then an oxide spacer 32 are formed on the sidewall of gate 26. Then, source/drain regions 28 are formed in the substrate 20, so as to perform heavily doping of ion implantation. Obviously, the gate width is fixed and is correspondent with effective channel length. Moreover, a small size of the semiconductor device is fabricated for producing a high speed semiconductor device. Thus, the effective channel length of the gate has to be reduced, but the length of the Metal-Oxide-Semiconductor device can not be unlimitedly reduced, because the length of channel is reduced to result in variable derivational problem. Hence, this phenomenon is called "Short Channel Effect".
As the device continuously shrinks to sub-quarter micron regime, since poly gate lithography is the key limitation, it is very difficult to keep good performance on Poly gate CD (Critical Dimension) control. By the way, Ti or Co silicide will be more difficult to form on sub-quarter micron, due to the line-width effect and shallow junction issue.
And yet, in accompanying with the shrinkage of devices, the thickness of the gate can be not too thick from the conventional process of the small size. If the thickness of the gate is too thick, it will result in the source/drain junction issue. Thicker silicon substrate is consumed at the source/drain region, when silicide is formed by means of using rapid thermal processing. Hence, results in shallower junctions. In order to avoid the formation of junctions leakage, the thickness of silicide layer at the source/drain region must be thinner enough as devices shrink in size.
When the size of the element is reduced, the surface joint in the source/drain must be shallow to match up with, so the short channel effect could be avoided. Moreover, the size of the gate is fixed within the conventional process, due to the overlapped channel can not be reduced. Herein, overlapped channel was formed by way of the source/drain extension at high temperature.
In deep sub-micron device fabrication, the process treats the salicide on the source/drain that is important and comprehensive application. The above can be accomplished by either using simple silicidation of source/drain. It will be difficult to deal with the salicide on the gate, while the size of the gate is considerably small.
In accordance with the above description, a new and improved method for fabricating the Metal-Oxide-Semiconductor device is therefore necessary, so as to raise the yield and quality of the follow-up process.